Explore jobs tagged with floorplanning to discover VLSI physical-design and chip-layout positions focused on floorplan optimization, placement strategies, and pre-PNR timing-closure workflows. This curated list of jobs (nav: jobs, pillar: tags) surfaces openings across semiconductor companies, design services, and EDA teams that require expertise in floorplanning methodologies, placement and routing trade-offs, power-area optimization, and industry tools such as Cadence Innovus and Synopsys ICC2. Use the filtering UI to narrow results by experience level, location, company, or related tags, review role requirements and example deliverables, and apply now with a targeted resume and portfolio demonstrating floorplan-driven design wins.
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