Physical Design EDA/CAD Engineer

About the Role

Requirements

• B.Sc. in Electrical Engineering Computer Engineering Computer Science or Practical Engineering (hands-on IC layout/CAD experience also considered)
• 1–3 years of relevant industry experience or 3+ years for more senior candidates
• Hands on experience with commercial and in-house layout and verification tools including Cadence Virtuoso Synopsys ICC and Mentor Calibre
• Strong programming skills in SKILL Python TCL Perl and Shell (Csh Bash)
• Ability to debug optimize and troubleshoot CAD flows and layout workflows
• Familiarity with regression testing code review flow validation and CI/CD practices in CAD/EDA environments
• Strong communication and teamwork skills and ability to work independently
• Preferred prior experience as a Layout Engineer or EDA/CAD Physical Design Engineer in a semiconductor environment
• Preferred deep understanding of IC physical design and verification flows including DRC LVS ERC parasitic extraction and tapeout readiness
• Preferred experience with PCells parameterized devices layout generators and physical verification runset programming
• Preferred experience building automated regression environments for CAD/EDA flows and in-house CAD tool development

Responsibilities

• Build maintain and optimize CAD tool infrastructure
• Develop and automate IC layout flows including placement routing floorplanning PCells and tapeout preparation
• Apply software engineering and CAD methodologies to deliver scalable automation solutions
• Collaborate with layout circuit and verification teams to capture requirements and deploy automation workflows
• Design and implement testing frameworks regression suites code review practices and CI/CD pipelines
• Define document and enforce best practices standards and procedures and provide technical guidance training and support

Skills